During the manufacture and handling of an integrated circuit, electrostatic discharges can occur at the terminals of the integrated circuit, instances of destruction occurring when the loading limit of the affected circuit section of the integrated circuit is exceeded. In order to afford protection from electrostatic discharges (ESD), therefore, an integrated circuit generally contains at least one ESD protection device. In order to determine the ESD strength of the integrated circuit, the integrated circuits processed on a wafer are singulated and from these individual circuits are selected and built up into a housing and then measured in a special ESD test unit. On account of the necessary construction of the integrated circuits and on account of the complex test methodology, times of several days to weeks are necessary in order to be able to determine the ESD strength on the basis of the integrated circuits.
Furthermore, loaded integrated circuits must not be passed to customers, and the loaded circuits are often destroyed in the course of determining the ESD strength, thus giving rise to high costs since the measurement conditions (high costs in the amperes range and pulse duration in the nano seconds range) are far from the standard operating conditions of the integrated circuits, special (expensive and difficult to control) measuring units are required for the measurement.
The latch-up strength of the integrated circuit (latch-up is understood to be the triggering of a parasitic thyristor) also has to be examined in a highly time-consuming manner, since the integrated circuit has to be singulated, built up and measured. Furthermore, the measured circuits in turn can generally no longer be used.
Since the methods described can only ever be used to examine individual integrated circuits in current production, the measurement results may, under certain circumstances, not be representative. In particular, results of one integrated circuit cannot be applied to other integrated circuits. This means that a statement about the ESD strength of the technology is also not possible. Even if the measurement results are representative and it is ascertained that the ESD/latch-up strength is insufficient, there is the difficulty that production has continued in the meantime (during the measurement time) and, consequently, a very large number of reject products have been produced. Furthermore, it is also extremely difficult to ascertain why the ESD/latch-up strength was insufficient and what process parameters are responsible for this. This often requires further, very complex examinations, as a result of which the time expenditure and costs increase further.
The document U.S. Pat. No. 5,523,252 describes a method for determining the electrostatic properties of an integrated circuit. In this case, a test component is provided and the power required to electrostatically destroy the test component is measured. In this case, the power is increased stepwise up to destruction.